Leakage is one of the biggest conditions limiting increased computer processor performance in modern processors. In semiconductor devices, leakage is a quantum phenomenon in which mobile charge carriers (e.g., electrons or holes) tunnel through an insulating region. Leakage increases exponentially as the thickness of the insulating region decreases. Tunneling leakage can also occur across semiconductor junctions between heavily doped P-type and N-type semiconductors. Other than tunneling via the gate insulator or junctions, carriers can also leak between source and drain terminals of a metal oxide semiconductor (MOS) transistor. Leakage primarily occurs inside transistors, but electrons can also leak between interconnects.
Leakage increases power consumption, and if sufficiently large, can cause complete circuit failure. In fact, increased leakage is a common source of circuit failure resulting from non-catastrophic overstress of a semiconductor device (i.e., when the junction or the gate oxide suffers damage that is permanent, but not sufficient to cause a catastrophic failure). Overstressing the gate oxide can lead to stress-induced leakage current.
Various approaches have been used to simulate and/or measure the leakage current of circuit designs. For instance, three-dimensional (3D) computer technology aided design (TCAD) can be used to accurately model a circuit and simulate the leakage paths therein, and Iddq testing can subsequently be used to measure the leakage. However, although 3D TCAD is highly accurate, this accuracy comes at the expense of time. It takes many hours to generate a complete model of a circuit in 3D TCAD; thus, this approach is not efficient when results are needed quickly.